Module Hardcaml.StructuralSource

Hardware generation API that includes tri-states - used for toplevel module generation.

The API is very similar to Signal except for instantiation which is done differently.

Sourcetype name = string
Sourcetype id = int
Sourcetype width = int
Sourcetype signal =
  1. | Empty
  2. | Module_input of id * name * width
  3. | Module_output of id * name * width * signal ref
  4. | Module_tristate of id * name * width * signal list ref
  5. | Internal_wire of id * width * signal ref
  6. | Internal_triwire of id * width * signal list ref
  7. | Instantiation_output of id * name
    (*

    reference to instantiation

    *)
  8. | Instantiation_tristate of id * name
  9. | Instantiation of id * name * (string * generic) list * (string * signal) list * (string * signal) list * (string * signal) list
  10. | Rtl_op of id * width * rtl_op
Sourceand rtl_op =
  1. | Constant of string
  2. | Select of int * int * signal
  3. | Concat of signal list
  4. | Mux of signal * signal list
Sourceand generic =
  1. | GInt of int
  2. | GFloat of float
  3. | GString of string
  4. | GUnquoted of string
Sourcetype circuit = {
  1. name : string;
  2. id : id;
  3. mutable signals : signal list;
}
Sourceexception Invalid_submodule_input_connection of string * string * signal
Sourceexception Invalid_submodule_output_connection of string * string * signal
Sourceexception Invalid_submodule_tristate_connection of string * string * signal
Sourceexception Wire_already_assigned of signal
Sourceexception Invalid_assignment_target of signal
Sourceexception Cant_assign_wire_with of signal
Sourceexception Cant_assign_triwire_with of signal
Sourceexception Invalid_name of signal
Sourceexception Invalid_width of signal
Sourceexception Invalid_id of signal
Sourceexception Invalid_constant of string
Sourceexception Rtl_op_arg_not_readable of signal
Sourceexception Too_few_mux_data_elements
Sourceexception Too_many_mux_data_elements of int
Sourceexception All_mux_data_elements_must_be_same_width of int list
Sourceexception No_elements_to_concat
Sourceexception Select_index_error of int * int
Sourceexception Binop_arg_widths_different of string
Sourceexception No_circuit
Sourceexception Circuit_already_started
Sourceval circuit : string -> unit

start circuit

Sourceval end_circuit : unit -> unit

complete circuit, add to database

Sourceval find_circuit : string -> circuit

find circuit in database

Sourceval width : signal -> int
Sourceval mk_input : string -> int -> signal
Sourceval mk_output : string -> int -> signal
Sourceval mk_tristate : string -> int -> signal
Sourceval mk_wire : int -> signal
Sourceval mk_triwire : int -> signal
Sourceval (<==) : signal -> signal -> unit
Sourceval is_connected : signal -> bool
Sourceval inst : ?g:(string * generic) list -> ?i:(string * signal) list -> ?o:(string * signal) list -> ?t:(string * signal) list -> string -> unit
Sourceval (==>) : 'a -> 'b -> 'a * 'b
Sourceval of_bit_string : string -> signal
Sourceval z : int -> signal
Sourceval mux : signal -> signal list -> signal
Sourceval concat_msb : signal list -> signal
Sourceval select : signal -> int -> int -> signal
Sourcemodule type Config = sig ... end
Sourceval prefix : string
Sourcemodule Base (C : Config) : Comb.Primitives with type t = signal

the comb API must be (rebuilt) between each circuit

Sourcemodule Base0 : Comb.Primitives with type t = signal

progressively more structural APIs

Sourcemodule Base1 : Comb.Primitives with type t = signal

includes mux, concat, select

Sourcemodule Base2 : Comb.Primitives with type t = signal

includes consts

Sourceval write_verilog : (string -> unit) -> circuit -> unit
Sourcemodule Lib : sig ... end