Module Hardcaml_of_verilogSource

Takes in a Hardcaml circuit and transforms it to a json file that can be read and rendered by netlistsvg.

Netlist representing a verilog design synthesized with yosys.

Static construction of an ocaml module with hardcaml interfaces that dynamically loads the implementation at runtime. Interface widths are adjusted based on instantiation parameters.

A data structure representing the hardcaml implementation of a Verilog_design.t converted to a Netlist.t.