Module Hardcaml_xilinxSource

Sourcemodule Byte_write_width : sig ... end
Sourcemodule Cascade_height : sig ... end

Height of BRAM cascades chains. This can be explicitly specified to help vivado meet timing when it is unnecessarily cascading BRAMs.

Sourcemodule Collision_mode : sig ... end
Sourcemodule Ram_arch : sig ... end

Xilinx RAM primitive types.

Sourcemodule Dual_port_ram : sig ... end

Single clock Dual Port Memory

Sourcemodule Fifo_async : sig ... end
Sourcemodule Fifo_sync : sig ... end
Sourcemodule Simple_dual_port_ram : sig ... end

Simple Dual Port Memory. 1 port is for writing, the other for reading.

Sourcemodule True_dual_port_ram : sig ... end

True Dual Port Memory with independent clocks for ports a and b.

Sourcemodule Ram_port : sig ... end
Sourcemodule Ram_port_with_clear : sig ... end

Statemachine for clearing a RAM via one of it's ports.

Sourcemodule Synthesis : sig ... end
Sourcemodule Memory_builder : sig ... end

A general-purpose means of representing memories. The Config.t type allows the user to configure the underlying memory implementations. Eg: Using URAM for bits 0-72, and BRAMs for bits 73-80. This module allows construction of memories in 1D or 2D Modes. See further documentation below.