Source file `simple_dual_port_ram.ml`

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
open Base
open Hardcaml
open Signal

let create
      ?read_latency
      ?arch
      ?(byte_write_width = Byte_write_width.Full)
      ?memory_optimization
      ?cascade_height
      ?simulation_name
      ~build_mode
      ()
      ~clock
      ~clear
      ~size
      ~write_address
      ~write_enable
      ~data
      ~read_address
      ~read_enable
  =
  let _, q =
    Dual_port_ram.create
      ?read_latency
      ?arch
      ?memory_optimization
      ?cascade_height
      ?simulation_name
      ~byte_write_width
      ~build_mode
      ()
      ~clock
      ~clear
      ~size
      ~port_a:{ Ram_port.write_enable; address = write_address; read_enable = gnd; data }
      ~port_b:
        { Ram_port.write_enable =
            (match byte_write_width with
             | Full -> gnd
             | B8 ->
               assert (width data % 8 = 0);
               zero (width data / 8)
             | B9 ->
               assert (width data % 9 = 0);
               zero (width data / 9))
        ; address = read_address
        ; read_enable
        ; data = zero (width data)
        }
  in
  q
;;