Source file `hardcaml_xilinx.ml`

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module Byte_write_width = Byte_write_width
module Cascade_height = Cascade_height
module Clocking_mode = Clocking_mode
module Collision_mode = Collision_mode
module Dual_port_ram = Dual_port_ram
module Fifo_async = Fifo_async
module Fifo_memory_type = Fifo_memory_type
module Fifo_sync = Fifo_sync
module Icape3 = Icape3
module Memory_builder = Memory_builder
module Ram_arch = Ram_arch
module Ram_port = Ram_port
module Ram_port_with_clear = Ram_port_with_clear
module Ram_with_resizing = Ram_with_resizing
module Simple_dual_port_ram = Simple_dual_port_ram
module Synthesis = Synthesis
module Sysmone1 = Sysmone1
module True_dual_port_ram = True_dual_port_ram