1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162openArch_declopenProgopenRiscv_declopenRiscv_extramoduletypeRiscv_input=sigvalcall_conv:(register,Arch_utils.empty,Arch_utils.empty,Arch_utils.empty,condt)calling_conventionendmoduleRiscv_core=structtypereg=registertyperegx=Arch_utils.emptytypexreg=Arch_utils.emptytyperflag=Arch_utils.emptytypecond=condttypeasm_op=Riscv_instr_decl.riscv_optypeextra_op=Riscv_extra.riscv_extra_optypelowering_options=Riscv_lowering.lowering_optionsletatoI=X86_arch_full.atoIriscv_declletasm_e=Riscv_extra.riscv_extraatoIletaparams=Riscv_params.riscv_paramsatoIletknown_implicits=[]letalloc_stack_need_extrasz=not(Riscv_params_core.is_arith_small(Conv.cz_of_zsz))(* FIXME RISCV: check if everything is ct *)letis_ct_asm_op(o:asm_op)=matchowith|_->trueletis_ct_asm_extra(o:extra_op)=trueletis_doit_asm_op(o:asm_op)=true(* All of the extra ops compile into DIT instructions only, but this needs to be checked manually. *)letis_doit_asm_extra(o:extra_op)=trueendmoduleRiscv(Lowering_params:Riscv_input):Arch_full.Core_archwithtypereg=registerandtyperegx=Arch_utils.emptyandtypexreg=Arch_utils.emptyandtyperflag=Arch_utils.emptyandtypecond=condtandtypeasm_op=Riscv_instr_decl.riscv_opandtypeextra_op=Riscv_extra.riscv_extra_op=structincludeRiscv_coreincludeLowering_paramsletlowering_opt=()letnot_saved_stack=(Riscv_params.riscv_liparamsatoI).lip_not_saved_stackletpp_asm=Pp_riscv.print_progletcallstyle=Arch_full.ByReg{call=SomeRA;return=true}end