Source file `verilog_base.ml`

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(* generated by dune *)

(** @canonical Verilog_base.V_fact *)
module V_fact = Verilog_base__V_fact

(** @canonical Verilog_base.V_label *)
module V_label = Verilog_base__V_label

(** @canonical Verilog_base.V_lib_base *)
module V_lib_base = Verilog_base__V_lib_base

(** @canonical Verilog_base.V_tree *)
module V_tree = Verilog_base__V_tree

(** @canonical Verilog_base.V_unparsing *)
module V_unparsing = Verilog_base__V_unparsing