Module Verilog_parsing.Parser_auxSource

module Fname = Langs_common.Fname
module Env_base = Langs_common.Env_base
Sourcemodule L = Label
Sourcetype vartype =
  1. | VTdefault
  2. | VTtype
Sourceand identifier_attribute =
  1. | IAclass of memtbl ref
  2. | IAcovergroup
  3. | IApackage
  4. | IAtype
  5. | IAproperty
  6. | IAclocking
  7. | IAextern_method
  8. | IAinterface
Sourceval iattr_to_str : identifier_attribute -> string
Sourceexception Attrs_found of identifier_attribute list
Sourcetype scope_attribute =
  1. | SApackage of Common.identifier
  2. | SAclass of Common.identifier
  3. | SAfunction of Common.identifier
  4. | SAother
Sourceval sattr_to_str : scope_attribute -> string
Sourceval create_frame : scope_attribute -> frame
Sourceval copy_frame : frame -> frame
Sourceval builtin_packages : (string * (string * identifier_attribute) list) list
Sourceval base_symbol_tbl : (Common.identifier, frame) Hashtbl.t
Sourceexception Frame_found of frame
Sourcetype state = {
  1. s_symbol_tbl : (Common.identifier, frame) Hashtbl.t;
  2. s_stack : frame Stack.t;
  3. s_scoped_flag : bool;
  4. s_pvstate : int;
  5. s_vartype : vartype;
  6. s_in_table : bool;
}
Sourceval mkstate : (Common.identifier, frame) Hashtbl.t -> frame Stack.t -> bool -> int -> vartype -> bool -> state
Sourceclass env : object ... end
Sourcemodule type STATE_T = sig ... end
Sourcemodule F (Stat : STATE_T) : sig ... end