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Module `Verilog_parsing.Scanner`Source

Sourcemodule Parserlib_base = Langs_common.Parserlib_base

Sourcemodule Astloc = Langs_common.Astloc

Sourcemodule Loc = Astloc

Sourcemodule Aux = Parser_aux

Sourcemodule PB = Parserlib_base

Sourcemodule TB = Tokenbuffer

Sourcemodule F (Stat : Aux.STATE_T) : sig ... end