Hardcaml_axi (p.hardcaml_axi.v0.16.0.doc.hardcaml_axi.Hardcaml

Module Hardcaml_axiSource

AXI4 Interface specifications.

See Xilinx User Guide ug1037 for full documentation.

Summary;

AXI4 is for memory-mapped interfaces and allows high throughput bursts of up to 256 data transfer cycles with just a single address phase.

AXI4-Lite is a light-weight, single transaction memory-mapped interface. It has a small logic footprint and is a simple interface to work with both in design and usage.

AXI4-Stream removes the requirement for an address phase altogether and allows unlimited data burst size. AXI4-Stream interfaces and transfers do not have address phases and are therefore not considered to be memory-mapped.

Sourcemodule type Bus_config = sig ... end

Sourcemodule type Stream_config = Stream.Config

Sourcemodule Address_space_decoder : sig ... end

Construction of address space decoders. This supports a slower but more complete full address space decoder and the faster but incomplete partial address decoder.

Sourcemodule Internal_bus : sig ... end

Sourcemodule Lite : sig ... end

AXI4-lite master/slave interface

Sourcemodule Lite_ports : sig ... end

Sourcemodule Stream : sig ... end

AXI4-stream source/dest interface.

Sourcemodule Register_bank : sig ... end

Sourcemodule Register_mode : sig ... end

Write configuration of a register from the core interface.

Sourcemodule Slave_with_data : sig ... end

Sourcemodule C_register_interface : sig ... end

C-code generators for a memory-mapped register space.