hardcaml_waveterm.kernel
Hardcaml_waveterm_kernel.Port
Simulation port description.
hardcaml_waveterm
hardcaml_waveterm.cyclesim
hardcaml_waveterm.event_store
hardcaml_waveterm.interactive
module Type : sig ... end
type t = {
type_ : Type.t;
port_name : Port_name.t;
width : Base.int;
}
include Ppx_compare_lib.Comparable.S with type t := t
val compare : t -> t -> int
val sexp_of_t : t -> Sexplib0.Sexp.t
include Ppx_compare_lib.Equal.S with type t := t
val equal : t -> t -> bool