Module V_label.StatementSource

include module type of struct include Ls.Statement end
Sourcetype t = Verilog_parsing.Labels.Statement.t =
  1. | Empty
  2. | OperatorAssignment of Verilog_parsing.Labels.AssignmentOperator.t
  3. | Labeled of Verilog_parsing.Common.identifier
  4. | BlockingAssignment
  5. | NonBlockingAssignment
  6. | Assign
  7. | Deassign
  8. | Force
  9. | Release
  10. | Case
  11. | Casex
  12. | Casez
  13. | Conditional
  14. | IncOrDec
  15. | SubroutineCall
  16. | SubroutineCallVoid
  17. | Disable
  18. | DisableFork
  19. | EventTrigger
  20. | EventTriggerNonBlocking
  21. | Forever
  22. | Repeat
  23. | While
  24. | For
  25. | Do
  26. | Foreach
  27. | Return
  28. | Break
  29. | Continue
  30. | ParBlock of Verilog_parsing.Common.identifier * Verilog_parsing.Labels.JoinSpec.t
  31. | ProceduralTimingControl
  32. | SeqBlock of Verilog_parsing.Common.identifier
  33. | Wait
  34. | WaitFork
  35. | WaitOrder
  36. | ProceduralAssertion
  37. | ClockingDrive
  38. | Randsequence of Verilog_parsing.Common.identifier
  39. | Randcase
  40. | ExpectProperty
  41. | Expr of Verilog_parsing.Labels.Expression.t
  42. | PExpr of Verilog_parsing.Labels.PropertyExpression.t
Sourceval to_string : t -> string
Sourceval to_simple_string : t -> Verilog_parsing.Common.identifier
Sourceval to_tag : t -> string * (string * Verilog_parsing.Common.identifier) list
Sourceval anonymize : t -> t
Sourceval to_short_string : ?ignore_identifiers_flag:bool -> t -> string