hardcaml
Cyclesim.Traced
ppx_hardcaml0
type io_port = {
signal : Signal.t;
name : Base.string;
}
val sexp_of_io_port : io_port -> Sexplib0.Sexp.t
type internal_signal = {
mangled_names : Base.string Base.list;
val sexp_of_internal_signal : internal_signal -> Sexplib0.Sexp.t
type t = {
input_ports : io_port Base.list;
output_ports : io_port Base.list;
internal_signals : internal_signal Base.list;
val sexp_of_t : t -> Sexplib0.Sexp.t
val to_io_port : Signal.t -> io_port