Cyclesim (p.hardcaml.v0.17.0.doc.hardcaml.Hardcaml.Cyclesim)

Sourcemodule Port_list : sig ... end

Sourcemodule Traced : sig ... end

Sourcemodule Node : sig ... end

Sourcemodule Reg : sig ... end

Sourcemodule Memory : sig ... end

Read and write access for memories. They have much the same API as Nodes. and Regs except for an extra address argument.

Sourcemodule Config : sig ... end

Sourcetype ('i, 'o) t

base type of the cycle based simulators

Sourcetype t_port_list = (Port_list.t, Port_list.t) t

Sourceval circuit : (_, _) t -> Circuit.t Base.option

returns the circuit used to compile the simulation.

Sourceval cycle : (_, _) t -> Base.unit

advance by 1 clock cycle (check->comb->seq->comb)

Sourceval cycle_check : (_, _) t -> Base.unit

check inputs are valid before a simulation cycle

Sourceval cycle_before_clock_edge : (_, _) t -> Base.unit

update combinatorial logic before clock edge and relative to new inputs.

Sourceval cycle_at_clock_edge : (_, _) t -> Base.unit

update sequential logic - registers and memories.

Sourceval cycle_after_clock_edge : (_, _) t -> Base.unit

update combinatorial logic after clock edge

Sourceval reset : (_, _) t -> Base.unit

reset simulator

Sourceval in_port : (_, _) t -> Base.string -> Bits.t Base.ref

get input port given a name

Sourceval traced : (_, _) t -> Traced.t

Signals and their unique (mangled) names to be traced by the simulation. Includes both IO ports and internal signals - the latter are accessible via the lookup function.

Sourceval out_port : ?clock_edge:Side.t -> (_, _) t -> Base.string -> Bits.t Base.ref

Get output port given a name. If clock_edge is Before the outputs are computed prior to the clock edge - After means the outputs are computed after the clock edge.

Sourceval inputs : ('i, _) t -> 'i

Sourceval outputs : ?clock_edge:Side.t -> (_, 'o) t -> 'o

Sourceval in_ports : (_, _) t -> Port_list.t

Sourceval out_ports : ?clock_edge:Side.t -> (_, _) t -> Port_list.t

Sourceval lookup_node : (_, _) t -> Traced.internal_signal -> Node.t Base.option

Current value of an internal (combinational) node within the simulator.

Sourceval lookup_node_by_name : (_, _) t -> Base.string -> Node.t Base.option

Source

val lookup_node_or_reg : 
  (_, _) t ->
  Traced.internal_signal ->
  Node.t Base.option

Sourceval lookup_node_or_reg_by_name : (_, _) t -> Base.string -> Node.t Base.option

Sourceval lookup_reg : (_, _) t -> Traced.internal_signal -> Reg.t Base.option

Peek at internal registers, return Some _ if it's present. Note that the node must marked as traced in Cyclesim.Config.t when creating simulations for this to return (Some _). Writing to the Bits.Mutable.t will change the simulation internal node's value and affect the results of simulation.

Sourceval lookup_reg_by_name : (_, _) t -> Base.string -> Reg.t Base.option

Sourceval lookup_mem : (_, _) t -> Traced.internal_signal -> Memory.t Base.option

Similar to lookup_data, but for memories. This is very useful for initializing memory contents without having to simulate the entire circuit.

Sourceval lookup_mem_by_name : (_, _) t -> Base.string -> Memory.t Base.option

Source

val create : 
  ?implementation:[ `V1 | `V2 ] ->
  ?config:Config.t ->
  Circuit.t ->
  t_port_list

construct a simulator from a circuit

Sourcemodule Combine_error : sig ... end

Source

val combine : 
  ?port_sets_may_differ:Base.bool ->
  ?on_error:(Combine_error.t -> Base.unit) ->
  ('i, 'o) t ->
  ('i, 'o) t ->
  ('i, 'o) t

Combine 2 simulators. The inputs are set on the 1st simulator and copied to the 2nd. Outputs are checked and on_error is called if a difference is found. By default, on_error raises.

The simulators should have the same input and output port sets, unless port_sets_may_differ is true, in which case only ports which exist on both simulators are checked.

Sourcemodule With_interface (I : Interface.S) (O : Interface.S) : sig ... end

Sourcemodule Private : sig ... end