Source file hardcaml__.ml

(* generated by dune *)

(** @canonical Hardcaml.Always *)
module Always = Hardcaml__Always

(** @canonical Hardcaml.Architecture *)
module Architecture = Hardcaml__Architecture

(** @canonical Hardcaml.Assertion_manager *)
module Assertion_manager = Hardcaml__Assertion_manager

(** @canonical Hardcaml.Assertions *)
module Assertions = Hardcaml__Assertions

(** @canonical Hardcaml.Async_fifo *)
module Async_fifo = Hardcaml__Async_fifo

(** @canonical Hardcaml.Bits *)
module Bits = Hardcaml__Bits

(** @canonical Hardcaml.Bits0 *)
module Bits0 = Hardcaml__Bits0

(** @canonical Hardcaml.Bits_intf *)
module Bits_intf = Hardcaml__Bits_intf

(** @canonical Hardcaml.Bits_list *)
module Bits_list = Hardcaml__Bits_list

(** @canonical Hardcaml.Bits_packed *)
module Bits_packed = Hardcaml__Bits_packed

(** @canonical Hardcaml.Build_mode *)
module Build_mode = Hardcaml__Build_mode

(** @canonical Hardcaml.Caller_id *)
module Caller_id = Hardcaml__Caller_id

(** @canonical Hardcaml.Circuit *)
module Circuit = Hardcaml__Circuit

(** @canonical Hardcaml.Circuit_database *)
module Circuit_database = Hardcaml__Circuit_database

(** @canonical Hardcaml.Circuit_utilization *)
module Circuit_utilization = Hardcaml__Circuit_utilization

(** @canonical Hardcaml.Clocking *)
module Clocking = Hardcaml__Clocking

(** @canonical Hardcaml.Clocking_intf *)
module Clocking_intf = Hardcaml__Clocking_intf

(** @canonical Hardcaml.Comb *)
module Comb = Hardcaml__Comb

(** @canonical Hardcaml.Comb_intf *)
module Comb_intf = Hardcaml__Comb_intf

(** @canonical Hardcaml.Combinational_op *)
module Combinational_op = Hardcaml__Combinational_op

(** @canonical Hardcaml.Combinational_ops_database *)
module Combinational_ops_database = Hardcaml__Combinational_ops_database

(** @canonical Hardcaml.Constant *)
module Constant = Hardcaml__Constant

(** @canonical Hardcaml.Cross_product *)
module Cross_product = Hardcaml__Cross_product

(** @canonical Hardcaml.Cross_product_intf *)
module Cross_product_intf = Hardcaml__Cross_product_intf

(** @canonical Hardcaml.Cyclesim *)
module Cyclesim = Hardcaml__Cyclesim

(** @canonical Hardcaml.Cyclesim0 *)
module Cyclesim0 = Hardcaml__Cyclesim0

(** @canonical Hardcaml.Cyclesim0_intf *)
module Cyclesim0_intf = Hardcaml__Cyclesim0_intf

(** @canonical Hardcaml.Cyclesim2 *)
module Cyclesim2 = Hardcaml__Cyclesim2

(** @canonical Hardcaml.Cyclesim2_ops *)
module Cyclesim2_ops = Hardcaml__Cyclesim2_ops

(** @canonical Hardcaml.Cyclesim_combine *)
module Cyclesim_combine = Hardcaml__Cyclesim_combine

(** @canonical Hardcaml.Cyclesim_compile *)
module Cyclesim_compile = Hardcaml__Cyclesim_compile

(** @canonical Hardcaml.Cyclesim_float_ops *)
module Cyclesim_float_ops = Hardcaml__Cyclesim_float_ops

(** @canonical Hardcaml.Cyclesim_float_ops_intf *)
module Cyclesim_float_ops_intf = Hardcaml__Cyclesim_float_ops_intf

(** @canonical Hardcaml.Cyclesim_intf *)
module Cyclesim_intf = Hardcaml__Cyclesim_intf

(** @canonical Hardcaml.Cyclesim_lookup *)
module Cyclesim_lookup = Hardcaml__Cyclesim_lookup

(** @canonical Hardcaml.Cyclesim_lookup_intf *)
module Cyclesim_lookup_intf = Hardcaml__Cyclesim_lookup_intf

(** @canonical Hardcaml.Cyclesim_schedule *)
module Cyclesim_schedule = Hardcaml__Cyclesim_schedule

(** @canonical Hardcaml.Dedup *)
module Dedup = Hardcaml__Dedup

(** @canonical Hardcaml.Design_rule_checks *)
module Design_rule_checks = Hardcaml__Design_rule_checks

(** @canonical Hardcaml.Edge *)
module Edge = Hardcaml__Edge

(** @canonical Hardcaml.Enum *)
module Enum = Hardcaml__Enum

(** @canonical Hardcaml.Enum_intf *)
module Enum_intf = Hardcaml__Enum_intf

(** @canonical Hardcaml.Fifo *)
module Fifo = Hardcaml__Fifo

(** @canonical Hardcaml.Fifo_intf *)
module Fifo_intf = Hardcaml__Fifo_intf

(** @canonical Hardcaml.Flags_vector *)
module Flags_vector = Hardcaml__Flags_vector

(** @canonical Hardcaml.Flags_vector_intf *)
module Flags_vector_intf = Hardcaml__Flags_vector_intf

(** @canonical Hardcaml.Hierarchy *)
module Hierarchy = Hardcaml__Hierarchy

(** @canonical Hardcaml.Instantiation *)
module Instantiation = Hardcaml__Instantiation

(** @canonical Hardcaml.Interface *)
module Interface = Hardcaml__Interface

(** @canonical Hardcaml.Interface_intf *)
module Interface_intf = Hardcaml__Interface_intf

(** @canonical Hardcaml.Level *)
module Level = Hardcaml__Level

(** @canonical Hardcaml.Logic *)
module Logic = Hardcaml__Logic

(** @canonical Hardcaml.Logic_intf *)
module Logic_intf = Hardcaml__Logic_intf

(** @canonical Hardcaml.Mangler *)
module Mangler = Hardcaml__Mangler

(** @canonical Hardcaml.Pair *)
module Pair = Hardcaml__Pair

(** @canonical Hardcaml.Pair_intf *)
module Pair_intf = Hardcaml__Pair_intf

(** @canonical Hardcaml.Parameter *)
module Parameter = Hardcaml__Parameter

(** @canonical Hardcaml.Parameter_name *)
module Parameter_name = Hardcaml__Parameter_name

(** @canonical Hardcaml.Ppx_hardcaml_runtime *)
module Ppx_hardcaml_runtime = Hardcaml__Ppx_hardcaml_runtime

(** @canonical Hardcaml.Property *)
module Property = Hardcaml__Property

(** @canonical Hardcaml.Property_manager *)
module Property_manager = Hardcaml__Property_manager

(** @canonical Hardcaml.Ram *)
module Ram = Hardcaml__Ram

(** @canonical Hardcaml.Read_port *)
module Read_port = Hardcaml__Read_port

(** @canonical Hardcaml.Reg_spec *)
module Reg_spec = Hardcaml__Reg_spec

(** @canonical Hardcaml.Reserved_words *)
module Reserved_words = Hardcaml__Reserved_words

(** @canonical Hardcaml.Rtl *)
module Rtl = Hardcaml__Rtl

(** @canonical Hardcaml.Rtl_ast *)
module Rtl_ast = Hardcaml__Rtl_ast

(** @canonical Hardcaml.Rtl_attribute *)
module Rtl_attribute = Hardcaml__Rtl_attribute

(** @canonical Hardcaml.Rtl_deprecated *)
module Rtl_deprecated = Hardcaml__Rtl_deprecated

(** @canonical Hardcaml.Rtl_intf *)
module Rtl_intf = Hardcaml__Rtl_intf

(** @canonical Hardcaml.Rtl_name *)
module Rtl_name = Hardcaml__Rtl_name

(** @canonical Hardcaml.Rtl_name_intf *)
module Rtl_name_intf = Hardcaml__Rtl_name_intf

(** @canonical Hardcaml.Rtl_verilog_of_ast *)
module Rtl_verilog_of_ast = Hardcaml__Rtl_verilog_of_ast

(** @canonical Hardcaml.Rtl_vhdl_of_ast *)
module Rtl_vhdl_of_ast = Hardcaml__Rtl_vhdl_of_ast

(** @canonical Hardcaml.Scalar *)
module Scalar = Hardcaml__Scalar

(** @canonical Hardcaml.Scalar_intf *)
module Scalar_intf = Hardcaml__Scalar_intf

(** @canonical Hardcaml.Scope *)
module Scope = Hardcaml__Scope

(** @canonical Hardcaml.Side *)
module Side = Hardcaml__Side

(** @canonical Hardcaml.Signal *)
module Signal = Hardcaml__Signal

(** @canonical Hardcaml.Signal__type *)
module Signal__type = Hardcaml__Signal__type

(** @canonical Hardcaml.Signal__type_intf *)
module Signal__type_intf = Hardcaml__Signal__type_intf

(** @canonical Hardcaml.Signal_graph *)
module Signal_graph = Hardcaml__Signal_graph

(** @canonical Hardcaml.Signal_intf *)
module Signal_intf = Hardcaml__Signal_intf

(** @canonical Hardcaml.Signedness *)
module Signedness = Hardcaml__Signedness

(** @canonical Hardcaml.Structural *)
module Structural = Hardcaml__Structural

(** @canonical Hardcaml.Structural_intf *)
module Structural_intf = Hardcaml__Structural_intf

(** @canonical Hardcaml.Topsort *)
module Topsort = Hardcaml__Topsort

(** @canonical Hardcaml.Types *)
module Types = Hardcaml__Types

(** @canonical Hardcaml.Value *)
module Value = Hardcaml__Value

(** @canonical Hardcaml.Value_intf *)
module Value_intf = Hardcaml__Value_intf

(** @canonical Hardcaml.Vcd *)
module Vcd = Hardcaml__Vcd

(** @canonical Hardcaml.Wave_data *)
module Wave_data = Hardcaml__Wave_data

(** @canonical Hardcaml.Wave_data_intf *)
module Wave_data_intf = Hardcaml__Wave_data_intf

(** @canonical Hardcaml.Wave_format *)
module Wave_format = Hardcaml__Wave_format

(** @canonical Hardcaml.With_valid *)
module With_valid = Hardcaml__With_valid

(** @canonical Hardcaml.With_valid_intf *)
module With_valid_intf = Hardcaml__With_valid_intf

(** @canonical Hardcaml.Write_port *)
module Write_port = Hardcaml__Write_port

(** @canonical Hardcaml.Zarith *)
module Zarith = Hardcaml__Zarith

module Hardcaml__ = struct end
[@@deprecated "this module is shadowed"]